The present invention relates to a nonvolatile ferroelectric random access memory; and, more particularly, to a method for generating a reference voltage in the ferroelectric random access memory of current gain cell mode.
A ferroelectric random access memory FeRAM, which is nonvolatile ferroelectric memory, has been spotlighted as a memory device of next generation since the FeRAM has a same data processing speed of a dynamic random access memory DRAM and has a nonvolatile characteristic, which preserves data without electric power.
FeRAM has similar structure of DRAM. That is, it is a memory device including a unit cell having 1 transistor 1 capacitor (1T1C) structure, which means the unit cell is constructed with one transistor and one capacitor. Also, FeRAM includes a ferroelectric capacitor in order to use high remnant characteristic of the ferroelectric. By using ferroelectric capacitor, data can be preserved when an electric field is eliminated.
FIG. 1 is a graph showing a characteristic of hysteresis loop of a conventional ferroelectric.
Referring to FIG. 1, although induced polarization eliminates the electric field, the electric field is not eliminated because of existence of remnant and a certain level of the electric field is maintained. The nonvolatile ferroelectric memory cell puts into practical use of a switching charge Q1 and non-switching charge Q0 of the ferroelectric for implementing a memory cell by mapping the Q1 to a logic xe2x80x981xe2x80x99 and the Q0 to a logic xe2x80x980xe2x80x99.
FIG. 2 is a circuit diagram illustrating a unit cell of conventional ferroelectric memory.
Referring to FIG. 2, the unit cell is formed by including a word line WL and a plate line PL formed in direction of row, a bit line formed in a direction of crossing the word line and plate line, a switching transistor TR having a gate connected to the word line WL, a-drain connected to the bit line BL, and a ferroelectric capacitor FC having one end connected to a source of the transistor TR, and another end connected to the plate line PL. A plurality of the above mentioned unit cells is constructed to a cell array unit.
In a mean time, for operating the ferroelectric memory, a reference voltage is required. For reading data stored in the unit cell, a data voltage transmitted to a main bit line BL needs to be compared with the reference voltage transmitted to a sub bit line /BL and to be amplified since the data voltage transmitted to the main bit line is so minute.
FIGS. 3A and 3B are circuit diagrams showing a conventional reference cell for generating a reference voltage in accordance with two different conventional methods.
Referring to FIG. 3A, the reference cell uses two cells having a ferroelectric capacitor, which is identical size of the capacitor in the memory cell, and a mean signal of a cell having data as xe2x80x981xe2x80x99 and other cell having data as xe2x80x980xe2x80x99 is used as a reference signal. In the FIG. 3A, RWL is a word line of the reference cell and RPL is a plate line of the reference cell.
The reference cell shown in FIG. 3A is required to have exact mean value of a cell having data as xe2x80x981xe2x80x99 and other cell having data as xe2x80x980xe2x80x99. However, it is impossible to provide exact mean value since degradation speeds of switching charge and non-switching charge of the ferroelectric capacitor are different.
For overcoming the above mentioned problem of the reference cell in FIG. 3A, different size of ferroelectric capacitor is used in reference cell of FIG. 3B comparing to a ferroelectric capacitor in a memory cell. It shows method generating non-switching charge as a reference signal by using larger ferroelectric capacitor in the reference cell comparing to the ferroelectric capacitor used in the memory cell.
However, the larger size of ferroelectric capacitor in FIG. 3B is more influenced by the capacitor degradation. Thus, it is not reliable method.
Recently, a FeRAM of current gain cell having hierarchy bit line structure has been introduced for improving a data sensing margin.
However, there is not method introduced for optimal reference voltage by overcoming the above mentioned problems to be suitable to the FeRAM having the current gain cell mode.
It is, therefore, an object of the present invention to provide a ferroelectric random access memory FeRAM for data sensing with simple peripheral circuit while constraining variation of reference voltage caused by degradation of a ferroelectric capacitor by implementing an identical size of ferroelectric capacitor in a memory cell and a reference cell and different size of NMOS transistor as current gain transistor in a memory cell and a reference cell.
In accordance with an aspect of the present invention, there is provided a ferroelectric memory device, including: a memory cell unit having hierarchical bit-line structure formed by forming a word line and a plate line in a direction of a row and forming sub-bit line and main bit line in a direction of crossing the word line and the plate line, and including a plural memory cells equipping a ferroelectric capacitor coupled to the sub bit line and a first current gain transistor having a gate coupled to the sub bit line, one end connected to a ground, and other end connected to the main bit line; a reference cell unit having hierarchical bit line structure formed by forming a reference word line and reference plate line in a direction of a row and forming a reference sub bit line and a reference main bit line in a direction of crossing the reference word line and reference plate line, and including a reference cell quipping a ferroelectric capacitor coupled to the reference sub bit line and a second current gain transistor having a gate connected to the reference sub bit line, an one end connected to a ground power supplying end and another end connected to the reference main bit line; and a sense amp unit for comparing voltages of the main bit line of the memory cell unit and the reference main bit line of the reference cell unit, amplifying the voltage difference and outputting data, wherein a size of the two ferroelectric capacitor in the memory cell and the reference cell is identical and a size of the first current gain transistor and the second current gain transistor is different.